View ADL5240-EVALZ_5198784.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

100 mhz to 4000 mhz rf/if digitally controlled vga adl5240 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features operating frequency from 100 mhz to 4000 mhz digitally controlled vga with serial and parallel interfaces 6-bit, 0.5 db digital step attenuator 31.5 db gain control range with 0.25 db step accuracy gain block amplifier specifications gain: 19.7 db at 2.14 ghz oip3: 41.0 dbm at 2.14 ghz p1db: 19.5 dbm at 2.14 ghz noise figure: 2.9 db at 2.14 ghz gain block or digital step attenuator can be first single supply operation from 4.75 v to 5.25 v low quiescent current of 93 ma thermally efficient, 5 mm 5 mm, 32-lead lfcsp the companion adl5243 integrates a ? w driver amplifier to the output of the gain block and dsa applications wireless infrastructure automated test equipment rf/if gain control general description the adl5240 is a high performance, digitally controlled variable gain amplifier (vga) operating from 100 mhz to 4000 mhz. the vga integrates a high performance, 20 db gain, internally matched amplifier (amp) with a 6-bit digital step attenuator (dsa) that has a gain control range of 31.5 db in 0.5 db steps with 0.25 db step accuracy. the attenuation of the dsa can be controlled using a serial or parallel interface. both the gain block and dsa are internally matched to 50 at their inputs and outputs and are separately biased. the separate bias allows all or part of the adl5240 to be used, which facilitates easy reuse throughout a design. the pinout of the adl5240 also enables either the gain block or dsa to be first, giving the vga maximum flexibility in a signal chain. the adl5240 consumes just 93 ma and operates from a single supply ranging from 4.75 v to 5.25 v. the vga is packaged in a thermally efficient, 5 mm 5 mm, 32-lead lfcsp and is fully specified for operation from ?40c to +85c. a fully populated evaluation board is available. functional block diagram adl5240 amp 9 nc 10 ampout/vcc 11 nc 12 nc 13 nc 14 nc 15 ampin 16 nc serial/parallel interface 24 vdd 23 nc 22 nc 21 dsaout 20 nc 19 nc 18 nc 17 nc 0.5db 1db 2db 4db 8db 16db 32 sel 31 d0/clk 30 d1/data 29 d2/le 28 d3 27 d4 26 d5 25 d6 1 vdd 2 nc 3 nc 4 dsain 5 nc 6 nc 7 nc 8 nc 09430-001 figure 1.
adl5240 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 8 ? esd caution.................................................................................. 8 ? pin configuration and function descriptions............................. 9 ? typical performance characteristics ........................................... 10 ? applications information .............................................................. 15 ? basic layout connections......................................................... 15 ? spi timing................................................................................... 17 ? loop performance...................................................................... 19 ? thermal considerations............................................................ 20 ? evaluation board ............................................................................ 21 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history 7/11revision 0: initial version
adl5240 rev. 0 | page 3 of 24 specifications vdd = 5 v, vcc = 5 v, t a = 25 o c table 1. parameter test conditions/comments min typ max unit overall function frequency range 100 4000 mhz amplifier frequency = 150 mhz using the ampin and ampout pins gain 17.6 db vs. frequency 50 mhz 1.0 db vs. temperature ?40c t a +85c 0.04 db vs. supply 4.75 v to 5.25 v 0.04 db input return loss s11 ?10.4 db output return loss s22 ?7.7 db output 1 db compression point 18.3 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 30.0 dbm noise figure 2.8 db amplifier frequency = 450 mhz using the ampin and ampout pins gain 20.3 db vs. frequency 50 mhz 0.11 db vs. temperature ?40c t a +85c 0.36 db vs. supply 4.75 v to 5.25 v 0.01 db input return loss s11 ?18.3 db output return loss s22 ?15.7 db output 1 db compression point 20.2 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 39.0 dbm noise figure 2.9 db amplifier frequency = 748 mhz using the ampin and ampout pins gain 20.6 db vs. frequency 50 mhz 0.01 db vs. temperature ?40c t a +85c 0.31 db vs. supply 4.75 v to 5.25 v 0.01 db input return loss s11 ?25.7 db output return loss s22 ?23.7 db output 1 db compression point 20.2 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 40.0 dbm noise figure 2.7 db amplifier frequency = 943 mhz using the ampin and ampout pins gain 19.0 20.5 22.0 db vs. frequency 18 mhz 0.01 db vs. temperature ?40c t a +85c 0.27 db vs. supply 4.75 v to 5.25 v 0.01 db input return loss s11 ?30.3 db output return loss s22 ?24.8 db output 1 db compression point 18.5 20.1 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 40.0 dbm noise figure 2.7 db
adl5240 rev. 0 | page 4 of 24 parameter test conditions/comments min typ max unit amplifier frequency = 1960 mhz using the ampin and ampout pins gain 19.8 db vs. frequency 30 mhz 0.03 db vs. temperature ?40c t a +85c 0.26 db vs. supply 4.75 v to 5.25 v 0.03 db input return loss s11 ?11.9 db output return loss s22 ?12.6 db output 1 db compression point 19.8 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 40.0 dbm noise figure 2.9 db amplifier frequency = 2140 mhz using the ampin and ampout pins gain 18.0 19.7 22.0 db vs. frequency 30 mhz 0.02 db vs. temperature ?40c t a +85c 0.25 db vs. supply 4.75 v to 5.25 v 0.04 db input return loss s11 ?11.0 db output return loss s22 ?12.0 db output 1 db compression point 17.5 19.5 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 41.0 dbm noise figure 2.9 db amplifier frequency = 2630 mhz using the ampin and ampout pins gain 18.0 19.6 22.0 db vs. frequency 60 mhz 0.01 db vs. temperature ?40c t a +85c 0.22 db vs. supply 4.75 v to 5.25 v 0.04 db input return loss s11 ?11.0 db output return loss s22 ?13.3 db output 1 db compression point 18.0 19.9 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 41.0 dbm noise figure 2.9 db amplifier frequency = 3600 mhz using the ampin and ampout pins gain 19.6 db vs. frequency 100 mhz 0.03 db vs. temperature ?40c t a +85c 0.05 db vs. supply 4.75 v to 5.25 v 0.10 db input return loss s11 ?15.1 db output return loss s22 ?12.2 db output 1 db compression point 18.8 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 37.0 dbm noise figure 3.1 db dsa frequency = 150 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?1.5 db vs. frequency 50 mhz 0.12 db vs. temperature ?40c t a +85c 0.09 db attenuation range 28.8 db attenuation step error all attenuation states 0.18 db attenuation absolute error all attenuation states 1.35 db input return loss minimum attenuation ?13.3 db output return loss minimum attenuation ?13.4 db input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 45.5 dbm
adl5240 rev. 0 | page 5 of 24 parameter test conditions/comments min typ max unit dsa frequency = 450 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?1.5 db vs. frequency 50 mhz 0.02 db vs. temperature ?40c t a +85c 0.10 db attenuation range 30.7 db attenuation step error all attenuation states 0.14 db attenuation absolute error all attenuation states 0.42 db input return loss minimum attenuation ?17.6 db output return loss minimum attenuation ?17.6 db input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 41.0 dbm dsa frequency = 748 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?1.6 db vs. frequency 50 mhz 0.02 db vs. temperature ?40c t a +85c 0.11 db attenuation range 30.9 db attenuation step error all attenuation states 0.15 db attenuation absolute error all attenuation states 0.32 db input return loss minimum attenuation ?17.4 db output return loss minimum attenuation ?17.4 db input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 40 dbm dsa frequency = 943 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?1.6 db vs. frequency 18 mhz 0.01 db vs. temperature ?40c t a +85c 0.12 db attenuation range 30.9 db attenuation step error all attenuation states 0.13 db attenuation absolute error all attenuation states 0.30 db input return loss minimum attenuation ?16.6 db output return loss minimum attenuation ?16.5 db input 1 db compression point minimum attenuation 30.5 dbm input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 48.5 dbm dsa frequency = 1960 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?2.4 db vs. frequency 30 mhz 0.02 db vs. temperature ?40c t a +85c 0.16 db attenuation range 31.0 db attenuation step error all attenuation states 0.15 db attenuation absolute error all attenuation states 0.29 db input return loss minimum attenuation ?12.0 db output return loss minimum attenuation ?11.5 db input 1 db compression point minimum attenuation 31.5 dbm input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 45.0 dbm dsa frequency = 2140 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?2.5 db vs. frequency 30 mhz 0.02 db vs. temperature ?40c t a +85c 0 .17 db attenuation range 31.0 db attenuation step error all attenuation states 0.12 db attenuation absolute error all attenuation states 0.26 db input return loss minimum attenuation ?11.9 db output return loss minimum attenuation ?11.2 db input 1 db compression point minimum attenuation 31.5 dbm input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 44.5 dbm
adl5240 rev. 0 | page 6 of 24 parameter test conditions/comments min typ max unit dsa frequency = 2630 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?2.6 db vs. frequency 60 mhz 0.04 db vs. temperature ?40c t a +85c 0.19 db attenuation range 31.2 db attenuation step error all attenuation states 0.16 db attenuation absolute error all attenuation states 0.19 db input return loss minimum attenuation ?13.1 db output return loss minimum attenuation ?12.0 db input 1 db compression point minimum attenuation 31.5 dbm input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 43.0 dbm dsa frequency = 3600 mhz using the dsain and dsaout pins insertion loss minimum attenuation ?2.8 db vs. frequency 100 mhz 0.03 db vs. temperature ?40c t a +85c 0.21 db attenuation range 32.1 db attenuation step error all attenuation states 0.37 db attenuation absolute error all attenuation states 0.31 db input return loss minimum attenuation ?20.2 db output return loss minimum attenuation ?18.2 db input 1 db compression point minimum attenuation 31.0 dbm input third-order intercept ?f = 1 mhz, p out = 4 dbm/tone, minimum attenuation 43.0 dbm digital step attenuator gain settling minimum attenuation to maximum attenuation 36 ns maximum attenuation to minimum attenuation 36 ns amp-dsa loop frequency = 943 mhz using the ampin and dsaout pins, dsa at minimum attenuation gain 18.9 db vs. frequency 18 mhz 0.01 db gain range between maximum and minimum attenuation states 30.8 db input return loss s11 ?20.5 db output return loss s22 ?19.7 db output 1 db compression point 18.6 dbm output third-order intercept ?f = 1 mhz, p out = 1 dbm/tone 36.0 dbm noise figure 2.7 db amp-dsa loop frequency = 2140 mhz using the ampin and dsaout pins, dsa at minimum attenuation gain 18.2 db vs. frequency 30 mhz 0.01 db gain range between maximum and minimum attenuation states 31.3 db input return loss s11 ?14.9 db output return loss s22 ?16.4 db output 1 db compression point 17.9 dbm output third-order intercept ?f = 1 mhz, p out = 1 dbm/tone 37.5 dbm noise figure 3.0 db
adl5240 rev. 0 | page 7 of 24 parameter test conditions/comments min typ max unit amp-dsa loop frequency = 2630 mhz using the ampin and dsaout pins, dsa at minimum attenuation gain 17.7 db vs. frequency 60 mhz 0.11 db gain range 31.5 db input return loss s11 ?15.2 db output return loss s22 ?9.6 db output 1 db compression point 16.9 dbm output third-order intercept ?f = 1 mhz, p out = 1 dbm/tone 33.7 dbm noise figure 3.0 db dsa-amp loop frequency = 943 mhz using the dsain and ampout pins, dsa at minimum attenuation gain 18.9 db vs. frequency 18 mhz 0.01 db gain range between maximum and minimum attenuation states 30.8 db input return loss s11 ?17.2 db output return loss s22 ?23.7 db output 1 db compression point 20.2 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 40.0 dbm noise figure 4.4 db dsa-amp loop frequency = 2140 mhz using the dsain and ampout pins, dsa at minimum attenuation gain 18.0 db vs. frequency 30 mhz 0.01 db gain range between maximum and minimum attenuation states 31.1 db input return loss s11 ?13.7 db output return loss s22 ?10.0 db output 1 db compression point 19.7 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 37.5 dbm noise figure 4.9 db dsa-amp loop frequency = 2630 mhz using the dsain and ampout pins, dsa at minimum attenuation gain 18.2 db vs. frequency 60 mhz 0.01 db gain range between maximum and minimum attenuation states 31.7 db input return loss s11 ?15.7 db output return loss s22 ?16.9 db output 1 db compression point 19.8 dbm output third-order intercept ?f = 1 mhz, p out = 4 dbm/tone 40.8 dbm noise figure 5.2 db power supplies using the vdd and vcc pins voltage 4.75 5.0 5.25 v supply current amplifier 93 120 ma digital step attenuator 0.5 ma
adl5240 rev. 0 | page 8 of 24 absolute maximum ratings table 2. parameter rating supply voltage (vdd, vcc) 6.5 v input power ampin 16 dbm dsain 30 dbm internal power dissipation 0.5 w ja (exposed pad soldered down) 36.8c/w jc (exposed pad is the contact) 6.9c/w maximum junction temperature 150c lead temperature (soldering, 60 sec) 240c operating temperature range ?40c to +85c storage temperature range ?65c to +150c esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
adl5240 rev. 0 | page 9 of 24 pin configuration and fu nction descriptions notes 1. nc = no connect. do not connect to this pin. 2 . the exposed pad must be connected to ground. pin 1 indicator 1 vdd 2 nc 3 nc 4 dsain 5 nc 6 nc 7 nc 8 nc 24 vdd 23 nc 22 nc 21 dsaout 20 nc 19 nc 18 nc 17 nc 9 n c 1 0 a m p o u t / v c c 1 1 n c 1 2 n c 1 3 n c 1 4 n c 1 5 a m p i n 1 6 n c 3 2 s e l 3 1 d 0 / c l k 3 0 d 1 / d a t a 2 9 d 2 / l e 2 8 d 3 2 7 d 4 2 6 d 5 2 5 d 6 top view (not to scale) adl5240 09430-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic description 1, 24 vdd supply voltage for dsa. connect this pin to a 5 v supply. 2, 3, 5, 6, 7, 8, 9, 11, 12, 13, 14, 16, 17, 18, 19, 20, 22, 23 nc no connect. do not connect to this pin. 4 dsain rf input to dsa. 10 ampout/vcc rf output from amplifier/supply voltage for ampl ifier. a bias to the amplifier is provided through a choke inductor connected to this pin. 15 ampin rf input to amplifier. 21 dsaout rf output from dsa. 25 d6 data bit in parallel mode (lsb). connect this pin to the supply in serial mode. 26 d5 data bit in parallel mode. connect this pin to ground in serial mode. 27 d4 data bit in parallel mode. connect this pin to ground in serial mode. 28 d3 data bit in parallel mode. connect this pin to ground in serial mode. 29 d2/le data bit in parallel mode /latch enable in serial mode. 30 d1/data data bit in parallel mode (msb)/data in serial mode. 31 d0/clk connect this pin to ground in parallel mo de. this pin functions as a clock in serial mode. 32 sel select pin. connect this pin to the supply to select parallel mode operation; connect this pin to ground to select serial mode operation. epad exposed pad. the exposed pad must be connected to ground.
adl5240 rev. 0 | page 10 of 24 typical performance characteristics 0 5 10 15 20 25 30 35 40 45 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 oip3 p1db gain nf noise figure, gain, p1db, oip3 (db, dbm) frequency (ghz) 09430-003 figure 3. amp: gain, p1db, oip3 at p out = 4 dbm/tone and noise figure vs. frequency 17.5 21.0 20.5 20.0 19.5 19.0 18.5 18.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 ?40c +25c +85c gain (db) frequency (ghz) 09430-004 figure 4. amp: gain vs. frequency and temperature ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 s12 s-parameters (db) frequency (ghz) s11 s22 09430-005 figure 5. amp: input return loss (s11), output return loss (s22), and reverse isolation (s12) vs. frequency 16 30 28 26 24 22 20 18 10 45 40 35 30 25 20 15 p1db (dbm) oip3 (dbm) frequency (ghz) 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 ?40c +25c +85c 09430-006 figure 6. amp: oip3 at p out = 4 dbm/tone and p1db vs. frequency and temperature 22 46 44 42 40 38 36 34 32 30 28 26 24 ?5 17 15 1311 97531 ?1?3 oip3 (dbm) p out per tone (dbm) 150mhz 450mhz 748mhz 943mhz 1960mhz 2140mhz 2630mhz 3600mhz 09430-007 figure 7. amp: oip3 vs. p out and frequency 1.5 2.0 2.5 3.0 3.5 4.0 4.5 04 3.63.22.82.42.0 1.61.2 0.80.4 noise figure (db) frequency (ghz) . 0 ?40c +25c +85c 09430-008 figure 8. amp: noise figure vs. frequency and temperature
adl5240 rev. 0 | page 11 of 24 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 4.13.73.32.92.52.1 1.71.3 0.90.5 attenuation (db) frequency (ghz) 0db 31.5db 09430-009 figure 9. dsa: attenuation vs. frequency ?36 ?31 ?26 ?21 ?16 ?11 ?6 ? 1 0.1 4.13.73.32.92.52.1 1.71.3 0.90.5 attenuation (db) frequency (ghz) 0db 4db 8db 16db 31.5db ?40c +25c +85c 09430-010 figure 10. dsa: attenuation vs. frequency and temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 03 2 28 2420 16 12 84 step error (db) attenuation (db) 450mhz 748mhz 943mhz 1960mhz 2140mhz 2630mhz 3600mhz 09430-011 figure 11. dsa: step error vs. attenuation ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 step error (db) frequency (ghz) 09430-016 31.5db 30.5db 16db 31db figure 12. dsa: step error vs. frequency, all attenuation states ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 03 2824 20 1612 84 absolute error (db) attenuation (db) 2 450mhz 748mhz 943mhz 1960mhz 2140mhz 2630mhz 3600mhz 09430-012 figure 13. dsa: absolute error vs. attenuation ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 4.1 0db 3.7 3.3 2.92.52.11.71.30.90.5 input return loss (db) frequency (ghz) 31.5db 09430-013 figure 14. dsa: input return loss vs. frequency, all states
adl5240 rev. 0 | page 12 of 24 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 4.1 0db 3.7 3.3 2.92.52.11.71.30.90.5 output return loss (db) frequency (ghz) 31.5db 09430-014 figure 15. dsa: output return loss vs. frequency, all states 30 31 32 33 34 35 36 20 25 30 35 40 45 50 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 ip1db (dbm) iip3 (dbm) frequency (ghz) iip3 ip1db 09430-015 figure 16. dsa: input p1db and input ip3 vs. frequency, minimum attenuation state ?150 ?100 ?50 0 50 100 150 200 0 4 8 12 16 20 24 28 32 phase (degrees) attenuation (db) 943mhz 1960mhz 2140mhz 2630mhz 09430-017 figure 17. dsa: phase vs. attenuation 09430-018 ch3 2.00v ch4 200mv m10ns 10gs/s it 1.0ps/pt a ch3 1.24v 3 4 figure 18. dsa: gain settling time, 0 db to 31.5 db 09430-019 ch3 2.00v ch4 200mv m10ns 10gs/s it 1.0ps/pt a ch3 1.24v 3 4 figure 19. dsa: gain settling time, 31.5 db to 0 db 0 22 20 18 16 14 12 10 8 6 4 2 0.1 4.13.7 3.3 2.92.52.11.71.30.90.5 gain and noise figure (db) frequency (ghz) gain noise figure 09430-020 figure 20. amp-dsa loop: gain and noise figure vs. frequency, minimum attenuation state
adl5240 rev. 0 | page 13 of 24 ?40 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 0.1 4.13.7 3.3 2.92.52.11.71.30.90.5 s-parameters (db) frequency (ghz) s11 s12 s22 09430-021 figure 21. amp-dsa loop: input return loss (s11), output return loss (s22), and reverse isolation (s12) vs. freq uency, minimum attenuation state 20 40 38 36 34 32 30 28 26 24 22 ?6 16 12 14 10 86420 ?2?4 oip3 (dbm) p out (dbm) 943mhz 2140mhz 2630mhz 09430-022 figure 22. amp-dsa loop: oip3 vs. p out and frequency, minimum attenuation state 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 ?4 20 12 14 16 18 10 86420 ?2 gain (db) p out (dbm) 943mhz 2140mhz 2630mhz 09430-023 figure 23. amp-dsa loop: gain vs. p out and frequency, minimum attenuation state 0 22 20 18 16 14 12 10 8 6 4 2 0.1 4.13.7 3.3 2.92.52.11.71.30.90.5 gain and noise figure (db) frequency (ghz) gain noise figure 09430-024 figure 24. dsa-amp loop: gain and noise figure vs. frequency, minimum attenuation state ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 4.1 s12 s-parameters (db) frequency (ghz) s11 s22 09430-025 figure 25. dsa-amp loop: input return loss (s11), output return loss (s22), and reverse isolation (s12) vs. freq uency, minimum attenuation state 24 44 38 40 42 36 34 32 30 28 26 ?6 16 12 14 10 86420 ?2?4 oip3 (dbm) p out (dbm) 943mhz 2140mhz 2630mhz 09430-026 figure 26. dsa-amp loop: oip3 vs. p out and frequency, minimum attenuation state
adl5240 rev. 0 | page 14 of 24 16.0 16.5 17.0 17.5 18.0 18.5 19.0 19.5 20.0 ?4 20 12 14 16 18 10 86420 ?2 gain (db) p out (dbm) 943mhz 2140mhz 2630mhz 09430-027 figure 27. dsa-amp loop: gain vs. p out and frequency, minimum attenuation state 80 110 105 100 95 90 85 ?40?30?20?100 102030405060708090 supply current (ma) temperature (c) 5.25v 5.00v 4.75v 09430-028 figure 28. amp: supply current vs. voltage and temperature 0 35 30 25 20 15 10 5 percentage (%) gain (db) 18.8 18.9 19.0 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.0 20.1 20.2 20.3 20.4 20.5 09430-029 figure 29. amp: gain distribution at 2140 mhz 0 30 25 20 15 10 5 percentage (%) p1db (dbm) 18.8 18.9 19.0 19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.0 20.1 20.2 20.3 20.4 20.5 09430-030 figure 30. amp: p1db distribution at 2140 mhz 0 30 25 20 15 10 5 percentage (%) oip3 (dbm) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 09430-031 figure 31. amp: oip3 distribution at 2140 mhz 0 70 60 50 40 30 20 10 percentage (%) noise figure (db) 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 09430-032 figure 32. amp: noise figure distribution at 2140 mhz
adl5240 rev. 0 | page 15 of 24 applications information basic layout connections the basic connections for operating the adl5240 are shown in figure 33 . nc vdd nc nc nc nc nc nc d1/data nc d2/le d3 d5 d4 dsaout nc nc d6 nc nc d0/clk sel ampin nc nc vdd dsain adl5240 nc nc nc nc serial parallel interface ampout/vcc 68pf 100pf 1.2nf 470nh vdd 100pf vdd 0.1f ampout dsain dsaout 0.1f ampin 1f vcc 0.1f c1 c2 c3 c4 c5 c6 c7 c8 l1 1 2 3 4 5 6 7 8 910 16 1514131211 24 23 22 21 20 19 18 17 32 31 252627 28 29 30 09430-033 figure 33. basic connections
adl5240 rev. 0 | page 16 of 24 amplifier bias the dc bias for the amplifier in adl5240 is supplied through inductor l1 and is connected to the ampout pin. three decoupling capacitors (c3, c4, and c5) are used to prevent rf signals from propagating onto the dc lines. the dc supply ranges from 4.75 v to 5.25 v and should be connected to the vcc test point on the evaluation board. digital step attenuator bias the bias for the dsa is provided through the vdd pin. at least one decoupling capacitor (c8) is recommended on the vdd trace. the voltage ranges from 4.75 v to 5.25 v and should be connected to the vdd test point on the evaluation board. the dsa is shown to work for dc voltages as low as 2.5 v. amplifier rf input interface pin 15 is the rf input for the amplifier of adl5240 . the amplifier is internally matched to 50 at the input; therefore, no external components are required. only a dc blocking capacitor (c1) is required. amplifier rf output interface pin 10 is the rf output for the amplifier of adl5240 . the amplifier is internally matched to 50 at the output; therefore, no external components are required. only a dc blocking capacitor (c2) is required. the bias is provided through this pin via a choke inductor. dsa rf input interface pin 4 is the rf input for the dsa of adl5240 . the input impedance of the dsa is close to 50 over the entire frequency range; therefore, no external components are required. only a dc blocking capacitor (c6) is required. dsa rf output interface pin 21 is the rf output for the dsa of adl5240 . the output impedance of the dsa is close to 50 over the entire frequency range; therefore, no external components are required. only a dc blocking capacitor (c7) is required. dsa spi interface the dsa of the adl5240 can operate in either serial or parallel mode. pin 32 (sel) controls the mode of operation. to select serial mode, connect sel to ground; to select parallel mode, connect sel to vdd. in parallel mode, pin 25 to pin 30 (d6 to d1) are the data bits, with d6 being the lsb. connect pin 31 (d0) to ground during the parallel mode of operation. in serial mode, pin 29 is the latch enable (le), pin 30 is the data (data), and pin 31 is the clock (clk). pin 26, pin 27, and pin 28 are not used in serial mode and should be connected to ground. pin 25 (d6) should be connected to vdd during the serial mode of operation. to prevent noise from coupling onto the digital signals, an rc filter can be used on each data line.
adl5240 rev. 0 | page 17 of 24 spi timing table 5 provides details about the timing characteristics for the spi signalsnamely, the clock (clk), latch enable (le), and data (data) signalsand figure 34 shows the corresponding spi timing diagram. spi timing sequence figure 35 is the timing sequence for the spi function using a 6-bit operation. the clock can be as fast as 20 mhz. in serial mode, register b5 (msb) is first and register b0 (lsb) is last. table 4. mode selection table pin 32 (sel) functionality connect to ground serial mode connect to supply parallel mode table 5. spi timing setup parameter limit unit test conditions/comments f clk 10 mhz data clock frequency t 1 30 ns min clock high time t 2 30 ns min clock low time t 3 10 ns min data to clock setup time t 4 10 ns min clock to data hold time t 5 10 ns min clock low to le setup time t 6 30 ns min le pulse width clk data le b4 b3 b1 msb b5 lsb b0 b2 t 6 t 5 t 1 t 2 t 4 t 3 09430-034 figure 34. spi timing diagram (data is loaded msb first), serial mode b4 b3 b1 msb b5 lsb b0 b2 d0/clk d1/dat a d2/le d6 09430-035 figure 35. spi timing sequence, serial mode
adl5240 rev. 0 | page 18 of 24 table 6. dsa attenuation truth tableserial mode attenuation state (db) b5 (msb) b4 b3 b2 b1 b0 (lsb) 0 (reference) 1 1 1 1 1 1 0.5 1 1 1 1 1 0 1.0 1 1 1 1 0 1 2.0 1 1 1 0 1 1 4.0 1 1 0 1 1 1 8.0 1 0 1 1 1 1 16.0 0 1 1 1 1 1 31.5 0 0 0 0 0 0 table 7. dsa attenuation truth tableparallel mode attenuation state (db) d1 (msb) d2 d3 d4 d5 d6 (lsb) 0 (reference) 1 1 1 1 1 1 0.5 1 1 1 1 1 0 1.0 1 1 1 1 0 1 2.0 1 1 1 0 1 1 4.0 1 1 0 1 1 1 8.0 1 0 1 1 1 1 16.0 0 1 1 1 1 1 31.5 0 0 0 0 0 0
adl5240 rev. 0 | page 19 of 24 loop performance the adl5240 can be configured so that either the dsa precedes the amplifier (see figure 36 ) or the amplifier precedes the dsa (see figure 37 ). the performance of the loop configurations is presented in figure 20 to figure 27 . to improve the overall return loss, a shunt capacitor can be placed between the amplifier and dsa. this helps to align the phases of the two blocks. nc vdd nc nc nc nc nc nc d1/data nc d2/le d3 d5 d4 dsaout nc nc d6 nc nc d0/clk sel ampin nc nc vdd dsain adl5240 nc nc nc nc serial parallel interface ampout/vcc 68pf 100pf 1.2nf 470nh vdd vdd 0.1f rfout rfin 100pf 1f vcc 0.1f c1 c2 c3 c4 c5 c6 c7 l1 1 2 3 4 5 6 7 8 910 16 1514 13 12 11 24 23 22 21 20 19 18 17 32 31 252627282930 09430-036 figure 36. dsa-amp loop configuration
adl5240 rev. 0 | page 20 of 24 nc vdd nc nc nc nc nc nc d1/data nc d2/le d3 d5 d4 dsaout nc nc d6 nc nc d0/clk sel ampin nc nc vdd dsain adl5240 nc nc nc nc serial parallel interface ampout/vcc 68pf 1.2nf 470nh vdd 100pf vdd 0.1f rfout 0.1f rfin 1f vcc c1 c3 c4 c5 c6 c7 c2 100pf l1 1 2 3 4 5 6 7 8 910 16 151413 12 11 24 23 22 21 20 19 18 17 32 31 252627282930 09430-037 figure 37. amp-dsa loop configuration thermal considerations the adl5240 is packaged in a thermally efficient, 5 mm 5 mm, 32-lead lfcsp. the thermal resistance from junction to air ( ja ) is 36.8 o c/w. the thermal resistance for the product was extracted assuming a standard 4-layer jedec board with 25 conductive, epoxy filled thermal vias. the thermal resistance from junction to case ( jc ) is 6.9 o c/w, where case is the exposed pad of the lead frame package. the adl5240 consumes approximately 93 ma with a 5 v supply voltage. even though the part dissipates less than 0.5 w, for the best thermal performance, it is recommended to add as many thermal vias as possible under the exposed pad of the lfcsp. the thermal resistance values given in this section assume a minimum of 25 thermal vias arranged in a 5 5 array with a diameter of 13 mils and a pitch of 25 mils. figure 38 shows a close-up of the thermal via distribution under the exposed pad. 09430-038 figure 38. exposed pad with thermal via distribution
adl5240 rev. 0 | page 21 of 24 evaluation board the schematic of the adl5240 evaluation board is shown in figure 39 , the evaluation board configuration options are detailed in table 8 , and the layout of the adl5240 evaluation board is shown in figure 40 and figure 41 . each rf trace on the evaluation board has a characteristic impedance of 50 and is fabricated on rogers3003 material. in addition, each trace is a coplanar waveguide (cpwg) with a width of 25 mils, a spacing of 20 mils, and a dielectric thickness of 10 mils. the input to and output from the dsa and amplifier should be ac-coupled with capacitors of appropriate values to ensure the broadband performance. the bias to the amplifier is provided by connecting a choke to the ampout pin. bypassing capacitors are recommended on all supply lines to minimize the rf coupling. the dsa and the amplifier can be individually biased or connected to the vdd plane using resistors r2 and r1. the adl5240 can be operated in two ways: the amplifier can precede the dsa (amp-dsa loop configuration) or the dsa can precede the amplifier (dsa-amp loop configuration). the evaluation board can be configured to handle either option. in normal operation, r12 and r13 are open, and r10 and r11 are 0 and are used to terminate any rf coupling onto the bypass trace. to configure the adl5240 in amp-dsa loop configuration, r12 should be replaced with a capacitor, r13 should be replaced with a 0 resistor, and r10 and r11 should be left open. similarly, to configure the adl5240 in the dsa-amp loop configuration, r16 should be replaced with a capacitor, r17 should be replaced with a 0 resistor, and r14 and r15 should be left open. the digital signal traces incorporate a footprint for an rc filter to prevent potential noise from coupling onto the signal. in normal operation, resistors r3 to r9 are 0 and capacitors c9 to c15 are open.
adl5240 rev. 0 | page 22 of 24 nc vdd nc nc nc nc nc nc d1 nc d2 d3 d5 d4 dsaout nc nc d6 nc nc d0 sel ampin nc nc vdd dsain adl5240 nc nc nc nc ampout/vcc r2 vdd 100pf 470nh 0.1f c2 0 0 0 0 dni dni dni dni dni dni 1 11 15 17 18 2 20 21 23 24 25 26 27 28 29 3 30 31 32 4 5 6 8 9 pad ampin 1 2 3 4 5 6 7 8 9 vdd 1 2 r9 c9 r8 r7 r6 r5 r4 r3 c10 c11 c13 c14 c15 clk data le c4 a mpout r17 0.1f dsain c1 19 dni dni dni 7 c12 0 0 0 0 dni dsaout 100pf l1 0.1f r12 13 r15 r14 c3 22 c8 3 dni r13 0 r10 r11 0 10 12 14 16 r16 dni 0 agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd 68pf 1.2nf vdd 1f r1 vcc c7 c6 c5 dni agnd s1 09430-039 figure 39. adl5240 evaluation board table 8. evaluation board configuration options component function/notes default value c1, c2 input/output dc blocking capacitors for dsa. c1, c2 = 100 pf c3, c4 input/output dc blocking capacitors for amp. c3, c4 = 0.1 f c5, c6, c7 power supply decoupling for amplifier. the bias associated with the ampout pin is the most sensitive to noise because the bias is connected directly to the output. the smallest capacitor (c7) should be the closest to the ampout pin. c5 = 1 f c6 = 1.2 nf c7 = 68 pf c8 power supply decoupling for the dsa. c8 = 0.1 f c9, c10, c11, c12, c13, c14, c15 capacitors of the rc filter on the digital signals leading to the spi chip. c9, c10, c11, c12, c13, c14, c15 = open l1 the bias for the amplifier comes through l1 when vcc is connected to a 5 v supply. l1 should be high impedance for the fr equency of operation while providing low resistance for the dc current. l1 = 470 nh r1, r2 resistors to connect the supply for the amplifier and the dsa to the same vdd plane. r1, r2 = open r3, r4, r5, r6, r7, r8, r9 resistors of the rc filter on the digital signals leading to the spi chip. r3, r4, r5, r6, r7, r8, r9 = 0 r10, r11, r14, r15 these resistors are used to terminate rf coupling onto the traces and to close the loop. r10, r11, r14, r15 = 0 r12, r13, r16, r17 r12 and r16 are replaced with capacitors, and r13 and r17 are replaced with 0 to close the loop. r12, r13, r16, r17 = open s1 switch to change between the serial mode and parallel mode of operation. connect to supply for parallel mode and to ground for serial mode operation. s1 connected to ground
adl5240 rev. 0 | page 23 of 24 09430-040 figure 40. evaluation board layouttop 09430-041 figure 41. evaluation board layoutbottom
adl5240 rev. 0 | page 24 of 24 outline dimensions 3.45 3.30 sq 3.15 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq 0.60 max 0.60 max 0.25 min 05-25-2011-a top view exposed pad bottom view figure 42. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adl5240acpz-r7 ?40c to +85c 32 lead lfcsp_vq, 7" tape and reel cp-32-3 ADL5240-EVALZ evaluation board 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09430-0-7/11(0)

▲Up To Search▲

Price & Availability of ADL5240-EVALZ

	To Download ADL5240-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .